The present invention relates to modulators/demodulators (modems) capable of simultaneous bilateral transmission (duplex) in the same frequency band, on a two-wire line.
As is known, a far-end echo canceller is used for reception in such modems.
The general arrangement of such a modem is, for example, illustrated in the figures appearing on pages 140 and 141 of Modem Data Book and Applications, first edition, May 1989, by SGS-THOMSON Microelectronics (ST). As is also known and indicated in the description associated with the above figures, an echo canceller generally comprises two channels, a channel for cancelling the near-end echoes associated with the emitter coupler and the parts close to the line, and a channel for cancelling far-end echoes corresponding, for example, to a transmission through one or several satellites. The far-end echo canceller must receive a signal corresponding to the transmitted signal delayed by the duration of the transmission and the echo on satellites, that is, for example, a duration of about one second. This implies the use of a delay line, in practice a memory, with a high storing size, for example, about 4k words for the above delay.
In a conventional modem architecture, a general-purpose microcontroller is provided; it can be constituted by the central processor of a personal computer to which the modem is coupled, especially comprising interface circuits with the data terminal equipment (DTE) transmitting and receiving data through the modem, a DTE control interpreter, data compression circuits, and error correction circuits. The specific functions of the modem, and especially the echo cancelling function, are achieved on one or several independent integrated circuits especially comprising a high-speed processor for achieving very fast calculations necessary to implement these functions. These circuits are commonly called data pump circuits.
More particularly, in conventional architectures, the data pump, ensuring the echo cancellation, has to be associated with the memory storing the transmitted signals. To be consistent with the remaining elements provided in the data pump, this memory is a high-speed memory, the access time of which is higher by several orders of magnitude than those required for a complete memory function, as, for example, those memories used in an SRAM-type memory, which occupies a relatively large surface. In numerous cases, for example, in the case of the above SGS-THOMSON circuit, this memory is constituted by an integrated circuit chip distinct from the data pump itself. In fact, a monolithic integration would generally involve the use of a chip with a too large surface.
This conventional architecture therefore exhibits several drawbacks.
A first drawback lies in the fact that, as indicated, the provision of a specific external memory is compulsory.
A second drawback, associated with the first, is that it is necessary to ensure an address and data link between the data pump and its external memory. When the memory has a 4k word size, it is to be noted that addressing must be made on at least 12 bits. This implies that 12 pads must be provided for this addressing, which increases the size of the data pump chip.